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| ASM3112C/4112C DATA SHEET ASM3112C/4112C ASM3112C/4112C - VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR 1.0 General Description The ASM3112C/4112C is very low cost voice synthesizer with 4-bit microprocessor. It has various features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog timer(WDT), voice synthesizer, etc. It consists of 22 instructions in the device. With CMOS technology and halt function can minimize power dissipation. Its architecture is similar to RISC, with two stages of instruction pipeline. It allows all instructions to be executed in a single cycle, except for program branches and data table read instructions (which need two instruction cycles). 1.1 Feature Single power supply can operate from 2.4V through 5.5V Internal Program ROM: 4K x 10-bit 1 sets of 17-bit DPR can access up to 128K x 10 bits data memory space Data Registers: * 96 x 4-bit data RAM (00-1Fh plus 40h-7Fh) * Unbanked special function registers (SFR) range: 20h-3Fh I/O Ports: * PRA: 4-bit I/O Port A (2Bh) * PRB: 4-bit Output Port B (2Dh) * PRC: 4-bit Input Port C (2Fh) On-chip clock generator: Resistive Clock Drive(RM) Timer: 1 * Timer0: a 9-bit auto-reload timer/counter Stack: 2-level subroutine nesting HALT and Release from HALT function to reduce power consumption Watch Dog Timer (WDT) Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles Number of instruction: 22 The Voice function can be implemented by microprocessor instruction * One 8-bit COUT output for ASM3112C/4112C 1 Rev 1.0 ASM3112C/4112C FIGURE 1.1 : Block Diagram of ASM3112C/4112C Data Bus[3:0] ROM Latch PCL(4) PC[11:0] (ADDR[16:12]) =0000b ADDR[16:0] Stack(12) (2-Level) 0 ROM_ADDR[16:0] 1 DPR3,2,1 DPR[16:0] Program (Data) ROM Instruction Latch Instruction Bus [9:0] Instruction Decoder PCLATCH(8) PCH(8) DLATCH(10) ROM_Data[9:0] Data Bus[3:0] Accumlator(4) Instruction Bus [9:0] SRAM ALU(4) Register(4) Immediate(4) (96 x 4) 00h-1Fh 40h-7Fh Timer0(9) PRA(4) PRB(4) PRC(4) P1,P2,P3,P4 enter test mode ( Voice synthesizer ) Clock Generator Test select Power on Reset RESET pin PRA0 weak or strong pull-low for PRA, PRB, PRC OSC VDD/GND PRASL(4) One-Channel Reset Chip Reset Chip COUT COUT 2 Rev 1.0 Instruction Bus [9:0] Control Signal ASM3112C/4112C FIGURE 1.2 : External ROM Map of ASM3112C/4112C PC[11:0] 12bit x 2 STACK 17-bit Data Pointer Reset Vector 00000h 00080h Reserved for Testing Program and data ROM 00080h-003FFh 00400h 00000h-00FFFh 00000h-1FFFFh 00FFFh(4K) Data ROM 1FFFFh(128Kx10-bits) 3 Rev 1.0 ASM3112C/4112C 1.2 Pin-Out ASM3112C/4112C Pin-Out PRC1 PRC0/RESET PRA3-1 PRA0/RESET I I I/O I/O STI Std./O.D. STI Std./O.D. STI Std./O.D. STI Std./O.D. Std./O.D. STI Std./O.D. Input port with programmable strong pull-low or weak pull-low or fix-input-floating capability Input port with programmable strong pull-low or weak pull-low or fix-input-floating capability Mask option selected as an external RESET pin with weak pull-low capability I/O port with programmable strong pull-low or weak pull-low or fix-input-floating capability Output type with standard or Open-Drain output I/O port with programmable strong pull-low or weak pull-low or fix-input-floating capability Output type with standard or Open-Drain output Mask option selected as an external RESET pin with weak pull-low capability RM mode Oscillator input First Power supply during operation Current Output of Audio First Circuit Ground Potential Second Circuit Ground Potential Enter Test Mode. ( TEST = High ) Second Power supply during operation Output type with standard or Open-Drain output Input port with programmable strong pull-low or weak pull-low or fix-input-floating capability OSC VDD1 COUT GND1 GND2 TEST VDD2 PRB0-3 PRC2-3 I I O I I O I O I 1.3 Application circuit 4 Rev 1.0 ASM3112C/4112C 1.4 Bonding Diagram 19 RC3 18 RC2 17 RC1 16 RC0 15 GND2 14 13 12 OSC VDD2 TEST ( 128K x 10-bit ) Block ROM ASM3112C/4112C RA3 RA2 RA1 RA0 VDD1 COUT GND1 RB0 RB1 RB2 RB3 1 2 3 4 5 6 7 8 9 10 11 Substrate must be connected to GND. ASM3112C/4112C Pad Location PAD # PAD Name X 1 RA3 -682.16 2 RA2 -559.84 3 RA1 -437.52 4 RA0 -315.2 5 VDD1 -191.28 6 COUT 71.12 7 GND1 189.52 8 RB0 307.92 9 RB1 430.24 10 RB2 552.56 Chip Size: X=1540+100 Y PAD # PAD Name -1040.2 11 RB3 -1040.2 12 OSC -1040.2 13 TEST -1040.2 14 VDD2 -1040.2 15 GND2 -1040.2 16 RC0 -1040.2 17 RC1 -1040.2 18 RC2 -1040.2 19 RC3 -1040.2 (um), Y=2320+100 (um) X Y 667.68 -1040.2 633.56 1071.52 432.48 1071.52 273.16 1071.52 134.68 1071.52 -51.76 1071.52 -248.4 1071.52 -454.24 1071.52 -650.88 1071.52 5 Rev 1.0 ASM3112C/4112C 1.5 DC Characteristics for ASM3112C/4112C SYMBOL VDD Isb Iop PARAMETER OPERATING VOLTAGE SUPPLY CURRENT STANDBY OPERATING VDD MIN. TYP. MAX. UNIT 2.4 3 5 3 5 3 5 5 3 5 3 5 -10 -20 3 5.5 1 1 2 7 3 9 -5.2 -3 -8 7 20 10 20 V uA mA CONDITION depending on Freq. 4MHz, RM in HALT Mode 4MHz, RM IO Floating 4MHz, RM in HALT Mode (IO Ports with weak pull-high pull-low) 4MHz, RM (IO ports) Fosc(3v- 2.4v) Fosc (3v) VDD=3V, Rosc=180k, 4MHz Iih INPUT CURRENT /Internal pull low OUTPUT HIGH CURRENT OUTPUT LOW CURRENT FREQUENCY STABILITY Fosc VARIATION uA Ioh Iol dF/F dF/F mA % % FIGURE 1.3 : Frequency Range for Rosc in RM mode Resistor(k ohm) 3v Freq.(MHz) 300 2.54 220 3.54 R osc & Freq. 180 3.99 150 5.49 6 5 4 3 2 1 0 0 100 5.49 3.99 3.54 2.54 Freq. MHz 200 R osc k ohm 300 400 6 Rev 1.0 |
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